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LijinWilson/README.md

Hi 👋, I'm Lijin Wilson

A passionate VLSI Engineer from India, highly motivated and growth-oriented with a strong drive for continuous learning and innovation in semiconductor design. Possessing proven ability to quickly grasp advanced VLSI concepts and EDA tools through self-study and hands-on projects, with a mindset dedicated to technical and professional growth. Skilled in managing complex design tasks, fostering collaboration, and coordinating effectively within teams to ensure project success. Known for excellent analytical and problem-solving skills, adaptability to new challenges, and applying innovative solutions in digital, analog, and mixed-signal design. Adept at using industry-standard tools such as Cadence Virtuoso, Xilinx Vivado, Visual TCAD, and Verilog/SystemVerilog for design and verification. Committed to achieving excellence in both individual contributions and team dynamics, with a relentless focus on delivering efficient, high-quality, and reliable VLSI solutions.

lijinwilson

  • 🔭 I’m currently learning Verilog, Perl, C, Python

  • 🌱 I'm having hand on experience in Cadence (Virtuoso, Assura), Xilinx Vivado, Visual TCAD**

  • 👨‍💻 All of my projects are available at GitHub

  • 💬 Ask me about (Virtuoso, Assura), Xilinx Vivado, Visual TCAD

  • 📫 How to reach me lijinwilson2018@gmail.com

  • 📄 Know about my experiences https://personalportfolio-blaze.vercel.app/

Connect with me:

https://www.linkedin.com/in/lijinwilson/

Languages and Tools:

angular verilog angular angular angular cadence cadence cadence

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  1. CMOS-Inverter CMOS-Inverter Public

    This repository contains the design, simulation, and analysis of a CMOS Inverter using industry-standard tools like Cadence Virtuoso. The project focuses on understanding and optimizing the fundame…

    1

  2. traffic-light-controller traffic-light-controller Public

    Traffic Light Controller This repository showcases the design and implementation of a Traffic Light Controller using Verilog. The project simulates a real-world traffic management system, ensuring …

    Verilog 1

  3. HDL_BIts_solving HDL_BIts_solving Public

    Answers for the hdl bits Verilog question

    Verilog 1

  4. CMOS-NAND-gate-2-input-NAND-gate CMOS-NAND-gate-2-input-NAND-gate Public

    This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics …

    1

  5. verilog-practice verilog-practice Public

    1