The circuit topology can't be changed once a simulation has been started. We could include the feature of adding and removing components during the simulation (mainly transient simulations).

I foresee the following difficulties:

• Adding/removing a component mid-simulation can cause convergence problems and a severe timestep truncation in transient analysis.
• Adding/removing a component in a time analysis would need to be timestamped. If the timestep is truncated to a moment before the component is added. The component should be temporarily removed then. Can be avoided when not using timestep truncation.
• Columns and rows need to be added/removed during simulation. This is not part of the current framework. This should be done carefully to avoid creating singular matrices.
• Integration states need to be added/removed during simulation. This is not part of the current framework.
• An added element would need some kind of initial condition.